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| lutton court, bernard terrace, edinburgh eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk wolfson microelectronics ? 1997 wolfson microelectronics wm8144-10 production data october 1997 rev. 3.0 integrated 10-bit data acquisition system for imaging applications description wm8144-10 integrates the analogue signal conditioning required by ccd sensors with a 10-bit adc and optional pixel-by-pixel image compensation. wm8144-10 requires minimal external circuitry and provides a cost effective sensor-to-digital domain system solution. each analogue conditioning channel provides reset level clamp, cds, fine offset level shifting and gain amplification. the three channels are multiplexed into the adc. output from the adc can either be direct or passed through a digital post-processing function. the post- processing provides compensation for variations in offset and shading on a pixel-by-pixel basis. the flexible output architecture allows ten-bit data to be accessed either on a ten-bit bus or via a time-multiplexed eight-bit bus. the wm8144-10 can be configured for pixel- by-pixel or line-by-line multiplexing operation. reset level clamp and/or cds features can be optionally bypassed. device configuration is either by a simple serial or eight- bit parallel interface. features block diagram ? reset level clamp ? correlated double sampling (cds) ? fine offset level shifting ? programmable gain amplification ? 10-bit adc with maximum 6 msps ? digital post-processing for pixel-by-pixel image compensation ? simple clocking scheme ? control by serial or parallel interface ? time-multiplexed eight-bit data output mode ? 48 pin tqfp package ? pin compatible with wm8144-12 applications ? document scanners ? ccd sensor interfaces ? contact image sensor (cis) interfaces production data data sheets contain fi- nal specifications current on publication date. supply of products conforms to wolfson microelectronics standard terms and conditions vsmp mclk rlc 10 bit adc image compensation processing external data store interface 10/8 mux configurable serial/parallel control interface v ru v rt v rb mux m u x v rl v mid v mid op[9:0] orng cdata(7:0) dv cc[2:0] sdi / dna pns sck / rnw sen / stb oeb v rlc a vdd a gnd d vdd1 d vdd2 d gnd timing control nreset s/h rinp cds cds cds s/h s/h ginp s/h s/h binp s/h wm8144-10 vs rs cl 8-bit + sign dac offset offset offset pga 5-bit reg v mid 8-bit + sign dac pga 5-bit reg v mid 8-bit + sign dac pga 5-bit reg v mid
wm8144-10 wolfson microelectronics 2 ordering information package outline recommended operating conditions parameter test conditions min typ max unit suppl y volta g e 4.75 5.25 v operatin g temperature ran g e t a 070 o c input common mode ran g e v cmr 0.5 4.5 v nc - make no external connection device temp range package wm8144-10c ft/v 0 0 c - 70 0 c48 pin tqfp absolute maximum ratings analogue supply voltage. . . agnd - 0.3 v, agnd +7 v digital supply voltage. . . . dgnd - 0.3 v, dgnd +7 v digital inputs . . . . . . . . dgnd - 0.3 v, dvdd + 0.3 v digital outputs. . . . . . . .dgnd - 0.3 v, dvdd + 0.3 v reference inputs . . . . . . agnd - 0.3 v, avdd + 0.3 v rinp, ginp, binp . . . . . .agnd - 0.3 v, avdd + 0.3 v operating temperature range, t a . . . . . 0 o c to +70 o c storage temperature . . . . . . . . . . -50 o c to +150 o c lead temperature (soldering, 10 sec) . . . . . . +260 o c note: absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating range limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. the wm8144-10 is manufactured on a cmos process. it is therefore generically sus- ceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. as per jedec specifications a112-a and a113-a this product requires specific storage conditions prior to surface mount assembly. it has been classified as having a moisture sensitivity level of 2 and as such will be supplied in vacuum sealed moisture barrier bags. 24 23 16 17 18 19 20 21 22 13 14 15 37 47 46 45 44 43 42 41 40 39 38 48 1 9 8 7 6 5 4 3 2 12 11 10 25 31 30 29 28 27 26 36 35 34 33 32 pns agnd ginp vrlc vmid binp rinp vru vrt vrb vrl avdd op2 dv nc nc dvdd2 op0 op1 cc2 cc1 cc0 orng nreset op3 op8 op7 op6 op5 op4 cdata3 cdata2 cdata1 cdata0 dgnd op9 cdata4 dvdd1 vsmp mclk cdata7 cdata6 cdata5 oeb sen/stb sdi/dna sck/rnw rlc wm8144-10 wm8144-10 wolfson microelectronics 3 electrical characteristics v dd = 4.75v to 5.25v, gnd = 0 v, ........t a = 0 o c to +70 o c, mlck = 12mhz unless otherwise stated. parameter test conditions min typ max unit suppl y current - active 110.0 150 ma suppl y current - standb y 10.0 15 ma digital inputs hi g h level input volta g ev ih 0.8*dvdd v low level input volta g ev il 0.2*dvdd v hi g h level input current i ih 1.0 m a low level input current i il 1.0 m a input capacitance 10.0 pf digital outputs hi g h level output volta g ev oh i oh = 1.0ma dvdd-0.75 v volta g e output ran g e v ol i ol = 1.0ma dgnd+0.75 v hi g h impedance output current i oz 1.0 m a input multiplexer channel to channel gain matchin g 0.5 % input video set-up time tvsu 10 ns input video hold time tvh 25 ns reset video set-up time trsu cds mode onl y 10 ns reset video hold time trh cds mode onl y 25 ns reference string reference volta g e - top v rt v ru = 5.00 v, v rl = 0.00v 3.465 3.5 3.535 v reference volta g e - bottom v rb v ru = 5.00 v, v rl = 0.00v 1.465 1.5 1.535 v dac reference volta g e v mid v ru = 5.00 v, v rl = 0.00v 2.475 2.5 2.525 v r.l.c. switch impedence 200 ohms reset level clamp options v rlc v ru = 5.00 v, v rl = 0.00v 1.425 1.5 1.575 v volta g e set b y user 2.375 2.5 2.625 v confi g uration - table 7 3.325 3.5 3.675 v impedance v rt to v rb 490 700 910 ohms impedance v ru to v rl 1190 1700 2210 ohms 8-bit dacs resolution 8 bits zero code volta g e v dac -10 v dac +10 mv full scale volta g e error 0 10 mv differential non linearit y dnl 0.1 1 lsb inte g ral non linearit y inl 0.4 1 lsb wm8144-10 wolfson microelectronics 4 electrical characteristics (contd.) v dd = 4.75v to 5.25v, gnd = 0 v, ........t a = 0 o c to +70 o c, mlck = 12mhz unless otherwise stated. note 1: guaranteed monotonic up to pga gain code 0fh note 2: guaranteed monotonic up to pga gain code 1fh parameter test conditions min typ max unit 10-bit adc resolution v dd = 5v 10 bits maximum samplin g rate v dd = 5v 6 msps full scale transition error volta g e at vinp dac code = 000h, v dd =5v, measured relative to vrt +/-50 +/-200 mv zero scale trans ition error volta g e at vinp dac code = 000h, v dd =5v, measured relative to vrb +/-50 +/-200 mv differential non linearit y dnl v dd = 5v -1 +1.25 lsb number of missin g c odes 0 code pga gain red channel max. gain, note 1 gr 12 mclk=12mhz; vdd=5v 4 times green channel max. gain, note 2 g g 12 mode=1 7 times blue channel max. gain, note 2 gb 12 7times red channel max. gain, note 2 gr 8 mclk=8mhz; vdd=5v 6 times green channel max. gain, note 2 g g 8 mode=1 7 times blue channel max. gain, note 2 gb 8 7times wm8144-10 wolfson microelectronics 5 electrical characteristics (contd.) v dd = 4.75v to 5.25v, gnd = 0 v, ........t a = 0 o c to +70 o c, mlck = 12mhz unless otherwise stated. parameter test conditions min typ max unit switching characteristics mclk period tper 83.3 ns mclk hi g h tckh 37.5 ns mclk low tckl 37.5 ns data set-up time tdsu 10 ns vsmp, rlc data hold time tdh 10 ns cdata data hold time tdh 30 ns output propa g ation dela y tpd i oh = 1.0ma 75 ns output enable time tpze i ol = 1.0ma 75 ns output disable time tpez 25 ns serial interface sck period tsper 83.3 ns sck hi g h tsckh 37.5 ns sck low tsckl 37.5 ns sdi set up time tssu 10 ns sdi hold time tsh 10 ns set up time - sck to sen tsce 20 ns set up time - sen to sck tsec 20 ns sen pulse width tsew 50 ns parallel interface rnw low to op [ 9:2 ] tristate topz 20 ns address setup time to stb low tasu 0 ns dna low setup time to stb low tadls 10 ns strobe low time tstb 50 ns address hold time from stb hi g h tah 10 ns dna low hold time from stb hi g h tadlh 10 ns data set-up t ime to stb low tdsu 0 ns dna hi g h setup time to stb low tadhs 10 ns data hold time from stb hi g h tdh 10 ns dna hi g h hold time from stb hi g h tadhh 10 ns rnw hi g h to op [ 9:2 ] output topd 0 ns wm8144-10 wolfson microelectronics 6 pin descriptions pin no. name type description 23 rinp analo g ue ip red channel input video 22 ginp analo g ue ip green channel input video 21 binp analo g ue ip blue channel input video 33 cdata [ 7 ] di g ital io ima g e compensation data read/write at twice adc conversion rate 34 cdata [ 6 ] di g ital io 35 cdata [ 5 ] di g ital io 36 cdata [ 4 ] di g ital io 37 cdata [ 3 ] di g ital io 38 cdata [ 2 ] di g ital io 39 cdata [ 1 ] di g ital io 40 cdata [ 0 ] di g ital io 32 mclk di g ital ip master c lock. this clock is applied at either six, four or two times the input pixel rate dependin g on the operational mode. mclk is divided internall y to define the adc s amples rate and to provide the clock sourc e for di g ital lo g ic. 31 vsmp di g ital ip video sample s y nchronisation pulse. this si g nal is applied s y nchronousl y with mlck to specif y the point in time that the input is sampled. the timin g of internal multiplexin g between the r, g and b channels is derived from this si g nal 29 rlc di g ital ip selects whether reset level clamp is applied on a pixel-b y -pixel basis. if rlc is re q uired on each pixel then this pin can be tied hi g h 19 v rlc analo g ue op selectable analo g ue output volta g e for rlc 13 v rt analo g ue ip adc referenc e volta g es. the adc referenc e ran g e is applied between 14 v rb analo g ue ip v rt ( full scale ) and v rb ( zer o level ) . v ru and v rl can be us ed to 15 v ru analo g ue ip derive optimum reference volta g es from an external 5v reference 16 v rl analo g ue ip 20 v mid analo g ue op buffered mid-point of adc reference strin g . 42 op [ 9 ] di g ital io tri-state di g ital 10-bit bi-directional bus. there are four modes: 43 op [ 8 ] di g ital io tri-state: when oeb = 1 44 op [ 7 ] di g ital io output ten-bit: ten bit data is output from bus 45 op [ 6 ] di g ital io output 8-bit multiplexed: data output on op [ 9:2 ] at 2*adc conversion rate 46 op [ 5 ] di g ital io input 8-bit: control data is input on bits op [ 9:2 ] 47 op [ 4 ] di g ital io 48 op [ 3 ] di g ital io 1op [ 2 ] di g ital io 2op [ 1 ] di g ital io 3op [ 0 ] di g ital io wm8144-10 wolfson microelectronics 7 pin descriptions (contd.) pin no. nam e type description 8cc [ 2 ] di g ital op colour code outputs. these outputs indicate from which channel the 9cc [ 1 ] di g ital op current output sample was taken ( r = 00x, g = 01x, b = 10x ) . 10 cc [ 0 ] di g ital op two codes are provided per channel. 11 orng di g ital op out-of-ran g e si g nal, active hi g h. this si g nal indicates that the current output pixel has exceeded the maximum or minimum achievable somewhere within the pixel processin g . 25 oeb di g ital ip output tri-state control, all outputs ( op [ 9:0 ] , dv, orng, cc [ 2: ]) enabled when oeb=0 7dv di g ital op data valid output, active low. 12 nreset di g ital ip reset input, active low. this si g nal forces a reset of all internal re g isters. 24 pns di g ital ip control interface parallel ( hi g h ) or serial ( low, default ) 27 sdi/dna di g ital ip serial interface: serial interface input data si g nal parallel interface: hi g h = data, low = address 28 sck/rnw di g ital ip serial interface: serial interface clock si g nal parallel interface: hi g h = op [ 9:2 ] is output, low = op [ 9:2 ] is input bus 26 sen/stb di g ital ip serial interface: enable, active hi g h parallel interface: strobe, active low 30 dvdd1 di g ital suppl y positive di g ital suppl y ( 5v ) 4dvdd2di g ital suppl y positive di g ital suppl y ( 5v ) 41 dgnd di g ital suppl y di g ital g round ( 0v ) 17 avdd analo g ue suppl y positive analo g ue suppl y ( 5v ) 18 agnd analo g ue suppl y analo g ue ground ( 0v ) 5 nc unused pin must be left unconnected 6 nc unused pin must be left unconnected wm8144-10 wolfson microelectronics 8 gai n dnl -5 -4 -3 -2 -1 0 1 2 3 4 5 012345678 ga i n red gr ee n blue mclk = 8mhz. input 2.5v +/- 100mv. other 2 are at 2.5v. colour. vdd = typical performance v dd = 5v, gnd = 0 v, ........t a = 25 o c. adc 10 bit dnl wm8144 10 bit dnl plot -1 -0.8 -0.6 -0.4 -0.2 0 0. 2 0. 4 0. 6 0. 8 1 0 25 6 51 2 76 8 10 24 adc code lsb's wm8144 10 bit inl plot -5 -4 -3 -2 -1 0 1 2 3 4 5 0 25 6 51 2 76 8 10 24 adc code lsb's pga ga in 0 1 2 3 4 5 6 7 8 012345678 ga i n red gr een blue mclk = 12.3mhz. input set to 2.5v +/- 100mv. other 2 are at 2.5v col o gai n dnl -5 -4 -3 -2 -1 0 1 2 3 4 5 012345678 ga i n red gr ee n blue mclk = 12.3mhz. input 2.5v +/- 100mv. other 2 are at 2.5v. colour. v d pga gai n 0 1 2 3 4 5 6 7 8 012345678 ga i n red gr een blue mclk = 8mhz. input set to 2.5v +/- 100mv. other 2 are at 2.5v colour. adc 10 bit inl pga dnl @ mclk = 12.3mhz pga dnl @ mclk = 8mhz pga gain code vs. actual gain @ mclk = 12.3mhz pga gain code vs. actual gain @ mclk = 8mhz actual gain pga gain code actual gain pga gain code dnl pga gain code dnl pga gain code adc code lsb's adc code lsb's wm8144-10 wolfson microelectronics 9 system diagram 10 bit adc image compensation logic control interface m u x integrated timing control v mid v mid v mid wm8144 red green blue optional external ram offset dac gain amps cds clamp simple two pin timing interface simple serial or parallel control interface ten bit image data at upto 6msps colour ccd sensor s/h s/h s/h s/h s/h s/h wm8144-10 wolfson microelectronics 10 s/h, offset dacs and pga each analogue input (rinp, ginp, binp) of the wm8144- 10 consists of a sample and hold, a programmable gain amplifier, and a dc offset correction block. the operation of the red input stage is summarised in figure 1. s/h s/h gain=g vs vmid vadc vmid voffset rinp rs - + + + figure 1 the sample/hold block can operate in two modes of op- eration, cds (correlated double sampling) or single ended. in cds operation the video signal processed is the differ- ence between the voltage applied at the rinp input when rs occurs, and the voltage at the rinp input when vs occurs. this is summarised in figure 2. rs vrs vvs vs figure 2 when using cds the actual dc value of the input signal is not important, as long as the signal extremes are main- tained within 0.5 volts of the chip power supplies. this is because the signal processed is the difference between the two sample voltages, with the common dc voltage being rejected. in single ended operation, the vs and rs control signals occur simultaneously, and the voltage applied to the re- set switch is fixed at v mid . this means that the voltage processed is the difference between the voltage applied to rinp when vs/rs occurs, and v mid . when using sin- gle ended operation the dc content of the video signal is not rejected. the programmable gain amplifier block multiplies the re- sulting input voltage by a value between 0.5 and 8.25 which can be programmed independently for each of the three input channels via the serial (or parallel) interface. pga gain is dependent on the 5-bit binary code pro- grammed in the pga registers. a typical plot of pga gain versus code is shown on page 8. the dc value of the gained signal can then be trimmed by the 8 bit plus sign dac. the voltage output by this dac is shown as voffset in figure 1. the range of the dac is (v mid /2). the output from the offset dac stage is referenced to the v mid voltage. this allows the input to the adc to maximise the dynamic range, and is shown diagrammati- cally in figure 1 by the final vmid addition. for the input stage the final analogue voltage applied to the adc can be expressed as: where: v adc is the voltage applied to the adc g is the programmed gain vvs is the voltage of the video sample vrs is the voltage of the reset sample sign is the offset dac sign bit dac_code is the offset dac value v mid is the wm8144-10 generated v mid voltage the adc has a lower reference of v rb (typically 1.5 v) and an upper reference of v rt (typically 3.5 v). when an adc input voltage is applied to the adc equal to vrb the resulting code is 000(hex). when an adc input volt- age is applied to the adc equal to v rt the resulting code is 3ff(hex). reset level clamp both cds and single ended operation can be used with reset level clamping. a typical input configuration is shown in figure 3. s/h s/h gain=g vs vmid vrlc rinp cin rs - + wm8144 figure 3 theory of operation () () vadc g vvs vrs 1 2 * sign * dac_ code 255 =-+- ? ? + * vmid vmid 2 wm8144-10 wolfson microelectronics 11 the position of the clamp relative to the video sample is programmable by cdsref1-0 (see table 7). by default, the reset sample occurs on the fourth mclk rising edge after vsmp. the relative timing between the reset sam- ple ( and cl) and video sample can be altered as shown in figure 4. figure 4: reset sample and clamp timing when the clamp pulse is active the voltage on the wm8144-10 side of cin, i.e. rinp, will be forced to be equal to the vrlc clamp voltage (see figure 5). the vrlc clamp voltage is programmable to three different levels via the serial interface (1.5v, 2.5v or 3.5v). the voltage to which the clamp voltage should be programmed is dependent on the type of sampling selected and the polarity of the input video signal. for cds operation it is important to match the clamp voltage to the amplitude and polarity of the video signal. this will allow the best use of the wide input common-mode range offered by the wm8144-10. if the input video is positive going it is ad- visable to clamp to vcl (lower clamp voltage). if the video is negative going it is advisable to clamp to vcu (upper clamp voltage). regardless of where the video is clamped the offset dac is programmed to move the adc output corresponding to the reset level to an appropriate value to maximise the adc dynamic range. for single ended operation it is recommended that the clamp voltage is set to vcm (middle clamp voltage). theory of operation (contd.) clamp pulse video input figure 5 a reset level clamp is activated if the rlc pin is high on an mclk rising edge (figure 6). by default this initiates an internal clamp pulse three mclk pulses later (figure 4: cl). the relationship between cl and rs is fixed. therefore altering the rs position also alters the cl po- sition (figure 4). table 7 shows the three possible voltages to which the reset level can be clamped. figure 6: rlc timing rinp, ginp and binp input impedence the input impedence of the wm8144-10 analogue inputs is dependent on the sampling frequency of the input sig- nal and the configuration of the internal gain amplifiers. the input impedence = 1/(capacitance * frequency) where the capacitance value changes from 0.3pf for minimum gain to 9.6pf for maximum gain. table 1 illus- trates the minimum and maximum input impedence at different frequencies. table 1: effects of frequency on input impedence sampling frequency (mhz) impedence with minimum gain (m w ) impedence with maximum gain (k w ) 0.5 6.6 208 1 3.3 104 21.6 52 40.8 26 60.5 17 wm8144-10 wolfson microelectronics 12 for a white pixel: v rs = v cl v vs = v cl - 1.6 for the white pixel, using the same offset dac value, the adc input can be expressed as: when the vmid is 2.5v, the adc input voltage becomes 1.7 volts which will result in a code of 102(dec). this is near the ideal full-scale of 000(dec). therefore the output codes from the adc are between 921(dec) and 102(dec), which implies that the adc input has been set up to maximise the dynamic range avail- able. if a digital representation of the adc output with a black level near 000(dec) and a white level near 1023(dec) is required then the invop control bit should now be set to one. theory of operation (contd) v = 1*(v - v ) + (1 - 2*0) * * + v adc cl cl mid v = 0 + * v + v adc mid mid v = * v adc mid 164 v mid 82 337 255 255 255 2 v = 1*(v - 1.6 - v ) + (1 - 2*0) * * + v adc cl cl mid v = -1.6 + * v + v adc mid mid v = * v - 1.6 adc mid 164 v mid 82 337 255 255 255 2 example of gain and offset operation input video polarity negative input sampling cds input voltage amplitude (v vs - v rs ) 1.6v programmable gain x1 clamping yes, v cl = 3.5v after the input capacitor the input to the wm8144-10 can be represented as: rs vrs vvs vs figure 7 for a black pixel: v rs = v cl v vs = v cl assuming that the offset dac is set to 00dec: ()() vadc = 1* vcl - vcl vadc 0 + 0 + vmid vadc = vmid +- ? ? + = 120 0 255 2 ** * vmid vmid vmid an input voltage of v mid corresponds to a code of 512(dec) from the adc. to maximise the dynamic range of the adc input it is necessary to program the offset dac code to move the adc code corresponding to the black level towards code 1024(dec). hence set the offset dac to 164(dec) with the sign bit not set. when the vmid is 2.5v, the adc input voltage becomes 3.3 volts which will result in an adc code of 921(dec). this is near the ideal full-scale of 1023(dec). wm8144-10 wolfson microelectronics 13 digital signal processing by default, the output from the adc passes through the digital compensation block without being altered and is output directly on the op[9:0] pins. if required, the pixel data from the adc can be processed further by the dig- ital compensation block (figure 8). this section describes the sub-blocks of the digital compensation block. cdata demultiplexor the input to this block is coefficient data presented to the cdata[7:0] pins at twice the pixel rate. i.e. two eight-bit words are input for each pixel of video data. data partitioning the sixteen bits of data per pixel from the cdata demultiplexor is partitioned into pixel offset, pixel gain and pixel valid bits (table 3) . table 4 details the resulting range and resolution options. pixel offset adder this uses the offset coefficients that are either supplied externally via the cdata interface or from the internal default registers. the object of this block is to correct for the small offsets which can occur from the ccd on a pixel-by-pixel basis. the output from the pixel offset adder is limited to be between 0 and 1023(dec). pixel gain adjust this block corrects for the pixel-by-pixel shading curve non-uniformity and photo response non-uniformity within the ccd sensor. this block has a gain range of 0 to 2. the output word from the pixel gain adjust is limited to between 0 and 1023(dec). effect of digital compensation on adc output the combined effect of the digital compensation sec- tions on the adc output is summarised by the formula: op[9:0] = (adcop + poc) * pscf where: all values are decimal op[9:0] is the 10 bit result output from the wm8144-10 adcop is a 10 bit unsigned number from the adc poc is a 2's compliment number divided bynumber of poc bits allocated/2 pscf is an unsigned number divided by number of psc bits allocated/2 for this example assume psc is allocated 12 bits and poc is allocated 4 bits (refer to table 3:dvmode,pwp0,pwp1 = 0). table 1 shows some ex- amples of the effect of the digital backend on the adc output. adcop poc psc op[9:0] orng range 0:1023 -8:7 0:4095 0:1023 0:1 default 0 2048 (x1) ex 1 512 0 2048 512 0 ex 2 512 -7 2048 505 0 ex 3 512 6 2048 518 0 ex 4 1022 6 2048 1023 1 ex 5 1022 6 512 257 1 ex 6 512 0 2560 640 0 ex 7 512 0 512 128 0 ex 8 512 0 4095 1023 1 ex 9 511 0 4095 1021 0 table 2: examples of digital backend calculation theory of operation (contd.) pixel offset adder limit mux mux mux default default mux pixel gain adjust limit data valid generation data partitioning demux and mux data latch out of range generation 10 11 4,5 or 6 612 10 12,11 or 10 22 10 10 adc orng input to 8/10 mux block op[9:0] input to 8/10 mux block dv output adcop cdata default figure 12 figure 8 wm8144-10 wolfson microelectronics 14 table 3: bit allocation assignment cdata word 1 cdata word 2 d v m o d e p w p 1 p w p 0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 g11 g10 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 o3 o2 o1 o0 0 0 1 g10g9g8g7g6g5g4g3g2g1g0o4o3o2o1o0 0 1 0 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 o5 o4 o3 o2 o1 o0 1 0 0 g10g9g8g7g6g5g4g3g2g1g0dvo3o2o1o0 1 0 1 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 dv o4 o3 o2 o1 o0 table 4: bit range and resolution options dvmode pwp1 pwp0 no. of offset bits offset range no. of gain bits gain range gain resolution (lsb s t eps) dv bits 0 0 0 4 -8 : 7 12 0:2 0.25 0 0 0 1 5 -16 - 15 11 0:2 0.5 0 0 1 0 6 -32 - 31 10 0:2 1 0 1 0 0 4 -8 - 7 11 0:2 0.5 1 1 0 1 5 -16 : 15 10 0:2 1 1 theory of operation (contd.) data valid generation the dv pin can be controlled to determine whether a dv pulse will be generated for a particular pixel. for exam- ple, if red pixels only are required the following dv pulse can be generated. b bg g rr op[9:0] dv figure 9 data latch under control of the latchop bit the output data bus can be prevented from clamping until the next data valid pulse. hence the above output would become: rr op[9:0] dv figure 10 output data interface by default, data is output from the device as a ten-bit wide word on op[9:0]. optionally, data can be output in an eight-bit word format. figure 11 shows this function. data is presented on pins op[9:2] at twice pixel rate. figure 11: eight-bit multiplexed bus output a = d9,d8,d7,d6,d5,d4,d3,d2 b = d1,d0,x,x,x,x,x,orng wm8144-10 wolfson microelectronics 15 operational modes video sampling options wm8144-10 can interface to ccd sensors using four basic modes of operation ( summarised in table 4). mode configurations are controlled by a combination of control bits and timing applied to mclk and vmsp pins. the de- fault operational mode is mode 1: colour with cds ena- bled. colour mode definition (mode 1) figure 12 summarises the timing relationships within the colour mode. mclk is applied at twice the required adc conversion rate. synchronisation of sampling and chan- nel multiplexing to the incoming video signal is performed by the vsmp pulse (active high). the three input chan- nels (r,g,b) are sampled in parallel on the rising edge of mclk following a vsmp pulse. the sampled data is mul- tiplexed into a single data stream at three times the vsmp rate and passes through the internal pipeline and emerges on the op[9:0] bus 20.5 mclk periods later. if the digital post-processing stage is activated, compen- sation data will be clocked into the device at twice the adc conversion rate (e.g. two reads per red pixel ). the first of the two bytes will be required on the cdata bus 15.5 mclk periods after the corresponding vsmp pulse. cc[2:0] can be used to control the three lower address lines of an external ram. both correlated double sam- pling (cds) and single sample modes of operation are available. monochrome mode definitions one input channel is continuously sampled on the rising edge of mclk following a vsmp pulse. the user can specify which input channel (r,g,b) to be sampled by writing to wm8144-10 internal control registers. there are three separate monochrome modes with different maximum sample rates and cds availability. details of monochrome mode timing (mode 2) figure 13 summarises the timing relationships. the tim- ing in this mode is identical to mode 1 except for the cc[2:0] outputs. one input channel is sampled three times ( due to the multiplexer being held in one position) and passes through the device as three separate sam- ples. two of the samples can be ignored at the output. the cc[2:1] output pins reflect the input channel selected (r,g or b). details of fast monochrome mode timing (mode 3) figure 14 summarises the timing relationships. this mode allows the maximum sample rate to be increased to 4 msps. this is achieved by altering the mclk:vsmp ratio to 3:1. in this mode, the timing of rs and cl must be fixed (refer to table 5). the sampled video data will pass through the internal pipeline and emerge on the op[9:0] bus 29.5 mclk periods later. if the digital post-processing stage is activated com- pensation data will be clocked into the device at twice the internal pixel rate (e.g. two reads per red pixel ). the first of the two bytes will be required on the cdata bus 22.5 mclk periods after the corresponding vsmp pulse. details of max. speed monochrome mode (mode 4) figure 15 summarises the timing relationships. this mode allows the maximum sample rate to be increased to 6 msps. this is achieved by altering the mclk:vsmp ratio to 2:1. the latency through the device is identical to modes 1 and 2. cds is not available in this mode. wm8144-10 wolfson microelectronics 16 table 5: wm8144-10 mode summary mode description cds available max. sample rate sensor interface description timing requirements register contents with cds* register contents without cds* 1 colour yes 2 msps the three input channels (r,g,b) are sampled in parallel at max. 2msps. the sampled data is multiplexed into a sin g le data stream before the internal adc g ivin g an internal serial data rate of max. 6msps. mclk max. 12mhz. mclk:vsmp ratio is 6:1. setup re g 1: 1b(h) setup re g 1: 19(h) 2 monochrome yes 2 msps one input channel is continuousl y sampled. the internal multiplexer is held in one position under control of the user. identical to mode 1 setup re g 1: 1f(h) setup re g 3: bits b[7-6] define which channel to be sampled setup re g 1: 1d(h) setup re g 3: bits b[7 - 6] define which channel to be sampled 3fast monochrome yes 4 msps identical to mode 2 mclk max. 12mhz. mclk:vsmp ratio is 3:1. identical to mode 2 plus setup re g 3: bits b[5-4] must be set to 00(h) identical to mode 2 4 max speed monochrome no 6 msps identical to mode 2 mclk max. 12mhz. mclk:vsmp ratio is 2:1. not applicable setup re g 1: 5d(h) setup re g 3: bits b[7 - 6] define which channel to be sampled * onl y indicates relevant re g ister bits operational modes (contd.) wm8144-10 wolfson microelectronics 17 device timing for mode 1 figure 12: default timing in cds colour mode adc input cdata[7:0] adc sample vs rs input video r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 vsmp mclk b0 g1 r1 20.5 mclk periods 15.5 mclk periods g2 r2 g3 r3 b1 r1 0 0 0 0 2 2 2 2 1 r1:1 r1:2 g1:1 g1:2 b1:1 b1:2 g1 1 1 1 1 b1 2 b2 b3 r4 g4 b4 1 2345 2345 op[9:0] cc[1] cc[0] dv orng cc[2] cc[2:1] input signals internal signals output signals operational modes (contd.) wm8144-10 wolfson microelectronics 18 device timing for mode 2 figure 13: default timing in cds monochrome mode cdata[7:0] adc sample vs rs input video r1,g1,b1 r2,g2,b2 r3,g3,b3 r4,g4,b4 r5,g5,b5 vsmp mclk 20.5 mclk periods r1 r1:1 r1:2 x x x xxx x x x x xx x x x x x x x x x x x x x x x x x 1 2345 2345 op[9:0]* cc[1]* cc[0] dv orng cc[2]* input signals internal signals output signals * this example shows function when red channel selected. cc[1] and cc[2] indicate the selected channel (r,g or b) 15.5 mclk periods 0000000000000 0 cc[2:1] adc input xxxx r1 x x xxx 'x' indicates don't care operational modes (contd.) wm8144-10 wolfson microelectronics 19 device timing for mode 3 figure 14: default timing in fast cds monochrome mode adc input cdata[7:0] adc sample vs rs input video n n:1 n n n:2 n+1 0 0 000000000 vsmp mclk 29.5 mclk periods 22.5 mclk periods op[9:0] cc[1]* cc[0] dv orng cc[2]* cc[2:1]* input signals internal signals output signals * this example shows function when red channel selected. cc[1] and cc[2] indicate the selected channel (r,g or b) operational modes (contd.) wm8144-10 wolfson microelectronics 20 device timing for mode 4 figure 15: default timing in max. speed non-cds monochrome mode operational modes (contd.) adc input cdata[7:0] adc sample vs input video vsmp mclk n 20.5 mclk periods 15.5 mclk periods n 0 0 0 000 00 00 00 0 0 n:1 n:2 1 op[9:0] cc[1]* cc[0] dv orng cc[2]* cc[2:1]* input signals internal signals output signals n * this example shows function when red channel selected. cc[1] and cc[2] indicate the selected channel (r,g or b) wm8144-10 wolfson microelectronics 21 figure 16: serial interface timing figure 17: parallel interface timing configuration of the wm8144-10 the wm8144-10 can be configured through a serial interface or a parallel interface. selection of the interface type is by the pns pin which must be tied high (parallel) or low (serial). serial interface the serial interface consists of three pins (refer to figure 16 ). a six-bit address is clocked in msb first followed by an eight-bit data word, also msb first. each bit is latched on the rising edge of sck, which can operate at upto 12mhz. once the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. parallel interface the parallel interface uses bits [9:2] of the op bus as well as the stb, dna and rnw pins (refer to figure 17). pin rnw must be low during a write operation. the dna pin defines whether the data byte is address (low) or data (high). the data bus op[9:2] is latched in during the low period of stb. this interface is compatible with the extended parallel port interface. internal register definition table 5 summarises the internal register content. the first 4 addresses in the table are used to program setup registers and to provide a software reset feature ( 00h is reserved ). the remaining 7 entries in the table define table 6: register map contents the address location of internal data registers. in each case, a further three sub-addresses are defined for the red, green and blue register. selection between the red, green and blue registers is performed by address bits a1 and a0, as defined in the table. setting both a1 and a0 equal to 1 forces all three registers to be updated to the same data value. blank entries can be taken as 'don't care' values. address description def'lt bit wm8144-10 wolfson microelectronics 22 configuration of the wm8144-10 (contd.) table 7: control bit descriptions register bit no bit(s) default description setup 0 enadc 1 adc standb y control: 0 = standb y , 1 = active re g ister 1 1 cds 1 select correlated double samplin g mode: 0 = normal samplin g , 1 = cds mode 2 mono 0 mono/colour select: 0 = colour, 1 = monochrome operation 3 defpg 1 select default pixel gain: 0 = external pixel g ain, 1 = internal 4 defpo 1 select default pixel offsets: 0 = external pixel offsets, 1 = internal 5 defdv 0 select default internal data valid: 0 = external dv, 1 = internal 6 vsmp6m 0 required when vsmp at 6msps: 0 = other mode, 1 = vsmp at 6msps 7 dvmode 0 external data valid control (refer to bit allocation assi g nment table) setup 0 muxop 0 ei g ht bit output mode: 0 = ten-bit, 1 = 8-bit multiplexed re g ister 2 1 2 invop 0 inverts adc output: 0 = non-invertin g , 1 = invertin g 3 latchop 0 op bus updated on dv pulse; op bus updated each sample, 1 = update onl y on dv pulse 4 bypass 0 b y pass di g ital post-processin g ; 0 = no b y pass, 1 = b y pass 5 cdatout 0 data on op pins available on cdat pins; 0 = no, 1 = y es 6 7 setup 1-0 rlc1-0 01 reset level clamp volta g e re g ister 3 00 = 1.5v 01 = 2.5v 10 = 3.5v 11 = reserved 3-2 pwp1-0 00 parallel word partitionin g see bit allocation assi g nment (table 3) 5-4 cdsref1-0 01 cds mode reset timin g ad j ust 00 = advance 1 mclk period 01 = normal 10 = retard 1 mclk period 11 = retard 2 mclk period 7-6 chan1-0 00 monochrome mode channel select 00 = red channel 01 = green channel 10 = blue channel 11 = reserved setup 1 dacrng 0 alters ran g e of offset dac output re g ister 4 0 = dac output ran g e equal to vmid/2 (1.25v) 1 = dac output ran g e equal to 1.5 * vmid/2 (1.875v) wm8144-10 wolfson microelectronics 23 figure 18: detailed video input timing - modes 1 and 2 figure 19: detailed digital timing - modes 1 and 2 detailed timing diagrams detailed timing diagrams wm8144-10 wolfson microelectronics 24 figure 22: detailed video input timing - mode 4 figure 23: detailed digital timing - mode 4 detailed timing diagrams (contd.) figure 20: detailed video input timing - mode 3 figure 21: detailed digital timing - mode 3 detailed timing diagrams (contd.) wm8144-10 wolfson microelectronics 25 figure 24: detailed timing diagram for serial interface detailed timing diagrams (contd.) t sckh t sckl t ssu t sh t sce t sew t sec t sper sck sdi sen rnw dna op[9:2] stb t opz 8144 out z address in t adls t asu t stb t adhs t adlh t dsu t ah data in t adhh t dh t stb t opd z 8144 out figure 25: detailed timing diagram for parallel interface wm8144-10 wolfson microelectronics 26 external component recommendations agnd 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 oeb sen/stb sdi/dna sck/rnw rlc dvdd1 vsmp mclk cdata7 cdata6 cdata5 cdata4 cdata3 cdata2 cdata1 cdata0 dgnd op9 op8 op7 op6 op5 op4 op3 pns rinp ginp binp vmid vrlc agnd avdd vrl vru vrb vrt c1 10 m f c2 0.1 m f c3 0.1 m f dgnd dgnd agnd avdd c7 33 m f c6 0.1 m f c5 22 m f c8 0.1 m f + + + wm8144-10 agnd c11 10 m f c10 0.1 m f c9 10 m f c12 ++ 0.1 m f nreset orng cc0 cc1 cc2 dv nc nc dvdd2 op0 op1 op2 c13 10 m f c14 0.1 m f dvdd + dvdd c15 10 m f c16 0.1 m f + dgnd wm8144-10 wolfson microelectronics 27 48 pin tqfp notes: a . all linear dimensions are in millimeters b. this drawing is subject to change without notice. c. falls within jedec mo-026 package dimensions 1.60max 1.45 1.35 0.08 seating plane 112 13 24 25 36 37 48 0.50 0.27 0.17 0.08 m 9.00 2 7.00 2 5.50typ 0.05min 0.25 0.75 0.45 0 o - 7 o 0.13nom gage plane |
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